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may 2008 ? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers FAN3223 / fan3224 / fan3225 dual 4a high-speed, low-side gate drivers features ? industry-standard pinouts ? 4.5 to 18v operating range ? 5a peak sink/source at v dd = 12v ? 4.3a sink / 2.8a source at v out = 6v ? choice of ttl or cmos input thresholds ? three versions of dual independent drivers: - dual inverting + enable (FAN3223) - dual non-inverting + enable (fan3224) - dual-inputs (fan3225) ? internal resistors turn driver off if no inputs ? millerdrive? technology ? 12ns / 9ns typical rise/fall times with 2.2nf load ? typical propagation delay under 20ns matched within 1ns to the other channel ? double current capability by paralleling channels ? 8-lead 3x3mm mlp or 8-lead soic package ? rated from ?40c to +125c ambient applications ? switch-mode power supplies ? high-efficiency mosfet switching ? synchronous rectifier circuits ? dc-to-dc converters ? motor control description the FAN3223-25 family of dual 4a gate drivers is designed to drive n-channel enhancement-mode mosfets in low-side switching applications by providing high peak current pulses during the short switching intervals. the driver is available with either ttl or cmos input thresholds. internal circuitry provides an under-voltage lockout function by holding the output low until the supply voltage is within the operating range. in addition, the drivers feature matched internal propagation delays between a and b channels for applications requiring dual gate drives with critical timing, such as synchronous rectifiers. this also enables connecting two drivers in parallel to effectively double the current capability driving a single mosfet. the fan322x drivers incorporate millerdrive? architecture for the final output stage. this bipolar- mosfet combination provides high current during the miller plateau stage of the mosfet turn-on / turn-off process to minimize switching loss, while providing rail- to-rail voltage swing and reverse current capability. the FAN3223 offers two inverting drivers and the fan3224 offers two non-inverting drivers. each device has dual independent enable pins that default to on if not connected. in the fan3225, each channel has dual inputs of opposite polarity, which allows configuration as non-inverting or inverting with an optional enable function using the second input. if one or both inputs are left unconnected, internal resistors bias the inputs such that the output is pulled low to hold the power mosfet off. FAN3223 fan3224 fan3225 figure 1. pin configurations
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 2 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers ordering information part number logic input threshold package packing method quantity per reel FAN3223cmpx 3x3mm mlp-8 tape & reel 3,000 FAN3223cmx cmos soic-8 tape & reel 2,500 FAN3223tmpx 3x3mm mlp-8 tape & reel 3,000 FAN3223tmx dual inverting channels + dual enable ttl soic-8 tape & reel 2,500 fan3224cmpx 3x3mm mlp-8 tape & reel 3,000 fan3224cmx cmos soic-8 tape & reel 2,500 fan3224tmpx 3x3mm mlp-8 tape & reel 3,000 fan3224tmx dual non-inverting channels + dual enable ttl soic-8 tape & reel 2,500 fan3225cmpx 3x3mm mlp-8 tape & reel 3,000 fan3225cmx cmos soic-8 tape & reel 2,500 fan3225tmpx 3x3mm mlp-8 tape & reel 3,000 fan3225tmx dual channels of two-input / one- output drivers ttl soic-8 tape & reel 2,500 all standard fairchild semiconductor products are rohs compliant and many are also ?green? or going green. for fairchild?s definition of ?green? please visit: http://www.fairchildsemi.com/com pany/green/rohs_green.html . package outlines figure 2. 3x3mm mlp-8 (top view) figure 3. soic-8 (top view) thermal characteristics (1) package jl (2) jt (3) ja (4) jb (5) jt (6) units 8-lead 3x3mm molded leadless package (mlp) 1.2 64 42 2.8 0.7 c/w 8-pin small outline integrated circuit (soic) 38 29 87 41 2.3 c/w notes: 1. estimates derived from thermal simulation; actual values depend on the application. 2. theta_jl ( jl ): thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a pcb. 3. theta_jt ( jt ): thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 4. theta_ja ( ja ): thermal resistance between junction and ambient, dependent on the pcb design, heat sinking, and airflow. the value given is for natural convection with no heatsink, as specified in jedec standards jesd51-2, jesd51-5, and jesd51-7, as appropriate. 5. psi_jb ( jb ): thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in note 4. for the mlp-8 package, the board reference is defined as the pcb copper connected to the thermal pad and protruding from either end of the package. for the soic-8 package, the board reference is defined as the pcb copper adjacent to pin 6. 6. psi_jt ( jt ): thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in note 4.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 3 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers FAN3223 fan3224 fan3225 figure 4. pin assignments (repeated) pin definitions name pin description ena enable input for channel a . pull pin low to inhibit driver a. ena has ttl thresholds for both ttl and cmos inx threshold. enb enable input for channel b . pull pin low to inhibit driver b. enb has ttl thresholds for both ttl and cmos inx threshold. gnd ground . common ground reference for input and output circuits. ina input to channel a . ina+ non-inverting input to channel a . connect to vdd to enable output. ina- inverting input to channel a . connect to gnd to enable output. inb input to channel b . inb+ non-inverting input to channel b . connect to vdd to enable output. inb- inverting input to channel b . connect to gnd to enable output. outa gate drive output a : held low unless required input(s) are present and v dd is above uvlo threshold. outb gate drive output b : held low unless required input(s) are present and v dd is above uvlo threshold. outa gate drive output a (inverted from the input): held low unless required input is present and v dd is above uvlo threshold. outb gate drive output b (inverted from the input): held low unless required input is present and v dd is above uvlo threshold. p1 thermal pad (mlp only). exposed metal on the bottom of the package; may be left floating or connected to gnd; not suitable for carrying current. vdd supply voltage . provides power to the ic. output logic FAN3223 ( x =a or b) fan3224 ( x =a or b) fan3225 ( x =a or b) enx inx outx enx inx outx inx+ inx ? outx 0 0 0 0 0 (7) 0 0 (7) 0 0 0 1 (7) 0 0 1 0 0 (7) 1 (7) 0 1 (7) 0 1 1 (7) 0 (7) 0 1 0 1 1 (7) 1 (7) 0 1 (7) 1 1 1 1 (7) 0 note: 7. default input signal if no external connection is made.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 4 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers block diagrams figure 5. FAN3223 block diagram figure 6. fan3224 block diagram
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 5 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers block diagrams figure 7. fan3225 block diagram
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 6 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd vdd to pgnd -0.3 20.0 v v en ena and enb to gnd gnd - 0.3 v dd + 0.3 v v in ina, ina+, ina?, inb, inb+ and inb? to gnd gnd - 0.3 v dd + 0.3 v v out outa and outb to gnd gnd - 0.3 v dd + 0.3 v t l lead soldering temperature (10 seconds) +260 oc t j junction temperature -55 +150 oc t stg storage temperature -65 +150 oc human body model, jedec jesd22-a114 4 kv esd electrostatic discharge protection level charged device model, jedec jesd22-c101 1 kv recommended operating conditions the recommended operating conditions table defines t he conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v dd supply voltage range 4.5 18.0 v v en enable voltage ena and enb 0 v dd v v in input voltage ina, ina+, ina?, inb, inb+ and inb? 0 v dd v t a operating ambient temperature -40 +125 oc
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 7 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers electrical characteristics unless otherwise noted, v dd =12v, t j =-40c to +125c. currents are defi ned as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit supply v dd operating range 4.5 18.0 v all except fan3225c 0.70 0.95 ma i dd supply current, inputs / en not connected fan3225c (8) 0.21 0.35 ma v on turn-on voltage ina=ena=vdd, inb=enb=0v 3.5 3.9 4.3 v v off turn-off voltage ina=ena=vdd, inb=enb=0v 3.3 3.7 4.1 v inputs (fan322xt) (9) v il_t inx logic low threshold 0.8 1.2 v v ih_t inx logic high threshold 1.6 2.0 v i in+ non-inverting input in from 0 to v dd -1.5 175.0 a i in- inverting input in from 0 to v dd -175.0 1.5 a v hys_t ttl logic hysteresis voltage 0.2 0.4 0.8 v inputs (fan322xc) (9) v il_c inx logic low threshold 30 38 %v dd v ih_c inx logic high threshold 55 70 %v dd i inl in current, low in from 0 to v dd -1 175 a i inh in current, high in from 0 to v dd -175 1 a v hys_c cmos logic hysteresis voltage 17 %v dd enable (FAN3223c, FAN3223t, fan3224c, fan3224t) v enl enable logic low threshold en from 5v to 0v 0.8 1.2 v v enh enable logic high threshold en from 0v to 5v 1.6 2.0 v v hys_t ttl logic hysteresis voltage (10) 0.4 v r pu enable pull-up resistance (10) 100 k ? t d1 , t d2 propagation delay, en rising (11) 0 - 5v in , 1v/ns slew rate 9 17 26 ns t d1 , t d2 propagation delay, en falling (11) 0 - 5v in , 1v/ns slew rate 11 18 28 ns continued on the following page?
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 8 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers electrical characteristics (continued) unless otherwise noted, v dd =12v, t j =-40c to +125c. currents are defi ned as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit output i sink out current, mid-voltage, sinking (10) out at v dd /2, c load =0.22f, f=1khz 4.3 a i source out current, mid-voltage, sourcing (10) out at v dd /2, c load =0.22f, f=1khz -2.8 a i pk_sink out current, peak, sinking (10) c load =0.22f, f=1khz 5 a i pk_source out current, peak, sourcing (10) c load =0.22f, f=1khz -5 a t rise output rise time (11) c load =2200pf 12 20 ns t fall output fall time (11) c load =2200pf 9 17 ns t d1 , t d2 output propagation delay, cmos inputs (11) 0 - 12v in , 1v/ns slew rate 10 18 29 ns t d1 , t d2 output propagation delay, ttl inputs (11) 0 - 5v in , 1v/ns slew rate 9 17 29 ns propagation matching between channels ina=inb, outa and outb at 50% point 2 4 ns i rvs output reverse current withstand (10) 500 ma notes: 8. lower supply current due to inactive ttl circuitry. 9. en inputs have ttl thresholds; refer to the enable section 10. not tested in production. 11. see timing diagrams of figure 8 and figure 9. timing diagrams figure 8. non-inverting figure 9. inverting
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 9 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 10. i dd (static) vs. supply voltage (12) figure 11. i dd (static) vs. supply voltage (12) figure 12. i dd (static) vs. supply voltage (12) figure 13. i dd (no-load) vs. frequency figure 14. i dd (no-load) vs. frequency
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 10 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 15. i dd (2.2nf load) vs. frequency figure 16. i dd (2.2nf load) vs. frequency figure 17. i dd (static) vs. temperature (12) figure 18. i dd (static) vs. temperature (12) figure 19. i dd (static) vs. temperature (12)
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 11 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 20. input thresholds vs. supply voltage figure 21. input thresholds vs. supply voltage figure 22. input threshold % vs. supply voltage figure 23. input threshol ds vs. temperature figure 24. input threshol ds vs. temperature
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 12 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 25. uvlo threshol ds vs. temperature figure 26. uvlo thres hold vs. temperature figure 27. propagation delay vs. supply voltage figure 28. propagation delay vs. supply voltage figure 29. propagation delay vs. supply voltage figure 30. propagation delay vs. supply voltage
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 13 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 31. propagation delays vs. temperature figure 32. propagation delays vs. temperature figure 33. propagation delays vs. temperature figure 34. propagation delays vs. temperature figure 35. fall time vs. supply voltage figure 36. rise time vs. supply voltage
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 14 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 37. rise and fall times vs. temperature figure 38. rise/fall waveforms with 2.2nf load figure 39. rise/fall waveforms with 10nf load figure 40. quasi-static source current with v dd =12v (13) figure 41. quasi-static sink current with v dd =12v (13)
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 15 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 42. quasi-static source current with v dd =8v (13) figure 43. quasi-static sink current with v dd =8v (13) notes: 12. for any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static i dd increases by the current flowing through the corresponding pu ll-up/down resistor shown in the block diagram. 13. the initial spike in each current waveform is a meas urement artifact caused by the stray inductance of the current-measurement loop. test circuit figure 44. quasi-static i out / v out test circuit
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 16 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers applications information input thresholds each member of the fan322x driver family consists of two identical channels that may be used independently at rated current or connected in parallel to double the individual current capacity. in the FAN3223 and fan3224, channels a and b can be enabled or disabled independently using ena or enb, respectively. the en pin has ttl thresholds for parts with either cmos or ttl input thresholds. if ena and enb are not connected, an internal pull-up resistor enables the driver channels by default. ena and enb have ttl thresholds in parts with either ttl or cmos inx threshold. if the channel a and channel b inputs and outputs are connected in paralle l to increase the driver current capacity, ena and enb should be connected and driven together. the fan322x family offers versions in either ttl or cmos input thresholds. in the fan322xt, the input thresholds meet industry- standard ttl-logic thresholds independent of the v dd voltage, and there is a hysteresis voltage of approximately 0.4v. these levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2v is considered logic high. the driving signal for the ttl inputs should have fast rising and falling edges with a slew rate of 6v/s or faster, so a rise time from 0 to 3.3v should be 550ns or less. with reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. in the fan322xc, the logic input thresholds are dependent on the v dd level and, with v dd of 12v, the logic rising edge threshold is approximately 55% of v dd and the input falling edge threshold is approximately 38% of v dd . the cmos input configuration offers a hysteresis voltage of approximately 17% of v dd . the cmos inputs can be used with relatively slow edges (approaching dc) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input voltage hysteresis window. this allows setting precise timing intervals by fitting an r-c circuit between the controlling signal and the in pin of the driver. the slow rising edge at the in pin of the driver introduces a delay between the controlling signal and the out pin of the driver. static supply current in the i dd (static) typical performance characteristics (figure 10 - figure 12 and figure 17 - figure 19) , the curve is produced with all inputs/enables floating (out is low) and indicates the lowest static i dd current for the tested configuration. for other states, additional current flows through the 100k resistors on the inputs and outputs shown in the block diagram of each part (see figure 5 - figure 7) . in these cases, the actual static i dd current is the value obtained from the curves plus this additional current. millerdrive? gate drive technology fan322x gate drivers incorporate the millerdrive? architecture shown in figure 45. for the output stage, a combination of bipolar and mos devices provide large currents over a wide range of supply voltage and temperature variations. the bipolar devices carry the bulk of the current as out swings between 1/3 to 2/3 v dd and the mos devices pull the output to the high or low rail. the purpose of the millerdrive? architecture is to speed up switching by providing high current during the miller plateau region when the gate-drain capacitance of the mosfet is being charged or discharged as part of the turn-on / turn-off process. for applications that have zero voltage switching during the mosfet turn-on or turn-off interval, the driver supplies high peak current for fast switching even though the miller plateau is not present. this situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the mosfet is switched on. the output pin slew rate is determined by v dd voltage and the load on the output. it is not user adjustable, but a series resistor can be added if a slower rise or fall time at the mosfet gate is needed. figure 45. millerdrive? output architecture under-voltage lockout the fan322x start-up logic is optimized to drive ground-referenced n-channel mosfets with an under- voltage lockout (uvlo) function to ensure that the ic starts up in an orderly fashion. when v dd is rising, yet below the 3.9v operational level, this circuit holds the output low, regardless of the status of the input pins. after the part is active, the supply voltage must drop 0.2v before the part shuts dow n. this hysteresis helps prevent chatter when low v dd supply voltages have noise from the power switching. this configuration is not suitable for driving high-side p-channel mosfets because the low output voltage of the driver would turn the p-channel mosfet on with v dd below 3.9v.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 17 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers vdd bypass capacitor guidelines to enable this ic to turn a device on quickly, a local high-frequency bypass capacitor c byp with low esr and esl should be connected between the vdd and gnd pins with minimal trace length. this capacitor is in addition to bulk electrolytic capacitance of 10f to 47f commonly found on driver and controller bias circuits. a typical criterion for choosing the value of c byp is to keep the ripple voltage on the v dd supply to 5%. this is often achieved with a value 20 times the equivalent load capacitance c eqv , defined here as q gate /v dd . ceramic capacitors of 0.1f to 1f or larger are common choices, as are dielectrics, such as x5r and x7r with good temperature characteristics and high pulse current capability. if circuit noise affects normal operation, the value of c byp may be increased to 50-100 times the c eqv , or c byp may be split into two capacitors. one should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10nf mounted closest to the vdd and gnd pins to carry the higher frequency components of the current pulses. the bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are switching simultaneously, the combined peak current sourced from the c byp would be twice as large as when a single channel is switching. layout and connection guidelines the FAN3223-25 family of gat e drivers incorporates fast-reacting input circuits, short propagation delays, and powerful output stages capable of delivering current peaks over 4a to facilitate voltage transition times from under 10ns to over 150ns. the following layout and connection guidelines are strongly recommended: ? keep high-current output and power ground paths separate logic and enable input signals and signal ground paths. this is especially critical when dealing with ttl-level logic thresholds at driver inputs and enable pins. ? keep the driver as close to the load as possible to minimize the length of high-current traces. this reduces the series inductance to improve high- speed switching, while reducing the loop area that can radiate emi to the driver inputs and surrounding circuitry. ? if the inputs to a channel are not externally connected, the internal 100k resistors indicated on block diagrams command a low output. in noisy environments, it may be necessary to tie inputs of an unused channel to vdd or gnd using short traces to prevent noise from causing spurious output switching. ? many high-speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output re- triggering. these effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. for best results, make connections to all pins as short and direct as possible. ? the fan322x is compatible with many other industry-standard drivers. in single input parts with enable pins, there is an internal 100k resistor tied to vdd to enable the driver by default; this should be considered in the pcb layout. ? the turn-on and turn-off current paths should be minimized, as discussed in the following section. figure 46 shows the pulsed gate drive current path when the gate driver is supplying gate charge to turn the mosfet on. the current is supplied from the local bypass capacitor, c byp , and flows through the driver to the mosfet gate and to ground. to reach the high peak currents possible, the resistance and inductance in the path should be minimized. the localized c byp acts to contain the high peak current pulses within this driver-mosfet circuit, preventing them from disturbing the sensitive analog circuitry in the pwm controller. figure 46. current path for mosfet turn-on figure 47 shows the current path when the gate driver turns the mosfet off. ideally, the driver shunts the current directly to the source of the mosfet in a small circuit loop. for fast turn-off times, the resistance and inductance in this path should be minimized. figure 47. current path for mosfet turn-off
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 18 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers truth table of logic operation the fan3225 truth table indicates the operational states using the dual-input configuration. in a non-inverting driver configuration, the in- pin should be a logic low signal. if the in- pin is connected to logic high, a disable function is realized, and the driver output remains low regardless of the state of the in+ pin. in+ in- out 0 0 0 0 1 0 1 0 1 1 1 0 in the non-inverting driver configuration in figure 48, the in- pin is tied to ground and the input signal (pwm) is applied to in+ pin. the in- pin can be connected to logic high to disable the driver and the output remains low, regardless of the state of the in+ pin. vdd gnd in- in+ out pwm fan3225 figure 48. dual-input driver enabled, non-inverting configuration in the inverting driver application in figure 49, the in+ pin is tied high. pulling the in+ pin to gnd forces the output low, regardless of the state of the in- pin. vdd gnd in- in+ out pwm fan3225 figure 49. dual-input driver enabled, inverting configuration operational waveforms at power-up, the driver output remains low until the v dd voltage reaches the turn-on threshold. the magnitude of the out pulses rises with v dd until steady-state v dd is reached. the non-inverting operation illustrated in figure 50 shows that the output remains low until the uvlo threshold is reached, then the output is in-phase with the input. figure 50. non-inverting start-up waveforms for the inverting configuration of figure 49, start-up waveforms are shown in figure 51. with in+ tied to vdd and the input signal applied to in?, the out pulses are inverted with respect to the input. at power- up, the inverted output remains low until the v dd voltage reaches the turn-on threshold, then it follows the input with inverted phase. vdd in+ (vdd) in- out turn-on threshold figure 51. inverting start-up waveforms
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 19 thermal guidelines gate drivers used to switch mosfets and igbts at high frequencies can dissipate significant amounts of power. it is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. the total power dissipation in a gate driver is the sum of two components, p gate and p dynamic : p total = p gate + p dynamic (1) gate driving loss: the most significant power loss results from supplying gate current (charge per unit time) to switch the load mosfet on and off at the switching frequency. the power dissipation that results from driving a mosfet at a specified gate- source voltage, v gs , with gate charge, q g , at switching frequency, f sw , is determined by: p gate = q g ? v gs ? f sw ? n (2) n is the number of driver channels in use (1 or 2). dynamic pre-drive / shoot-through current: a power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the ?i dd (no-load) vs. frequency? graphs in typical performance characteristics to determine the current i dynamic drawn from v dd under actual operating conditions: p dynamic = i dynamic ? v dd ? n (3) once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming jb was determined for a similar thermal design (heat sinking and air flow): t j = p total ? jb + t b (4) where: t j = driver junction temperature jb = (psi) thermal characterization parameter relating temperature rise to total power dissipation t b = board temperature in location as defined in the thermal characteristics table. to give a numerical example, if the synchronous rectifier switches in the forward converter of figure 52 are fdms8660s, the datasheet gives a total gate charge of 60nc at v gs = 7v, so two devices in parallel would have 120nc gate charge. at a switching frequency of 300khz, the total power dissipation is: p gate = 120nc ? 7v ? 300khz ? 2 = 0.5w (5) p dynamic = 1.5ma ? 7v ? 2 = 0.021w (6) p total = 0.52w (7) the soic-8 has a junction-to-board thermal characterization parameter of jb = 42c/w. in a system application, the localized temperature around the device is a function of the layout and construction of the pcb along with airflow across the surfaces. to ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150c; with 80% derating, t j would be limited to 120c. rearranging equation 4 determines the board temperature required to maintain the junction temperature below 120c: t b,max = t j - p total ? jb (8) t b,max = 120c ? 0.52w ? 42c/w = 98c (9) for comparison, replace the soic-8 used in the previous example with the 3x3mm mlp package with jb = 2.8c/w. the 3x3mm mlp package could operate at a pcb temperature of 118c, while maintaining the junction temperature below 120c. this illustrates that the physically smaller mlp package with thermal pad offers a more conductive path to remove the heat from the driver. consider tradeoffs between reducing overall circuit size with junction temperature reduction for increased reliability.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 20 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers typical application diagrams figure 52. high current forward converter with synchronous rectification figure 53. center-tapped bridge output with synchronous rectifiers pwm-a pwm-b pwm-c pwm-d secondary phase shift controller vin qa qb qc qd sr-2 sr-1 fan3224 fan3227 fan3227 figure 54. secondary controlled full bridge with current doubler output, synchronous rectifiers (simplified)
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 21 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers table 1. related products part number type gate drive (14) (sink/src) input threshold logic package fan3100c single 2a +2.5a / -1.8a cmos single channel of two-input/one-output sot23-5, mlp6 fan3100t single 2a +2.5a / -1.8a ttl single channel of two-input/one-output sot23-5, mlp6 fan3226c dual 2a +2.4a / -1.6a cmos dual inverting channels + dual enable soic8, mlp8 fan3226t dual 2a +2.4a / -1.6a ttl dual inverting channels + dual enable soic8, mlp8 fan3227c dual 2a +2.4a / -1.6a cmos dual non-inverting channels + dual enable soic8, mlp8 fan3227t dual 2a +2.4a / -1.6a ttl dual non-inverting channels + dual enable soic8, mlp8 fan3228c dual 2a +2.4a / -1.6a cmos dual channels of two-input/one-output, pin config.1 soic8, mlp8 fan3228t dual 2a +2.4a / -1.6a ttl dual channels of two-input/one-output, pin config.1 soic8, mlp8 fan3229c dual 2a +2.4a / -1.6a cmos dual channels of two-input/one-output, pin config.2 soic8, mlp8 fan3229t dual 2a +2.4a / -1.6a ttl dual channels of two-input/one-output, pin config.2 soic8, mlp8 FAN3223c dual 4a +4.3a / -2.8a cmos dual inverting channels + dual enable soic8, mlp8 FAN3223t dual 4a +4.3a / -2.8a ttl dual inverting channels + dual enable soic8, mlp8 fan3224c dual 4a +4.3a / -2.8a cmos dual non-inverting channels + dual enable soic8, mlp8 fan3224t dual 4a +4.3a / -2.8a ttl dual non-inverting channels + dual enable soic8, mlp8 fan3225c dual 4a +4.3a / -2.8a cmos dual channels of two-input/one-output soic8, mlp8 fan3225t dual 4a +4.3a / -2.8a ttl dual channels of two-input/one-output soic8, mlp8 note: 14. typical currents with out at 6v and v dd = 12v.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 22 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers physical dimensions b. dimensions are in millimeters. c. dimensions and tolerances per a. conforms to jedec registration mo-229, variation veec, dated 11/2001 asme y14.5m, 1994 recommended land pattern 0.05 0.00 2x 2x 0.8 max seating plane d. filename: mkt-mlp08drev2 figure 55. 3x3mm, 8-lead molded leadless package (mlp) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 23 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers physical dimensions (continued) 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge figure 56. 8-lead soic package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN3223 / fan3224 / fan3225 ? rev. 1.0.5 24 FAN3223 / fan3224 / fan3225 ? dual 4a high-speed, low-side gate drivers

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